Crossing the Synchronous-Asynchronous Divide

The increasing complexity of modern VLSI systems has caused designers to reevaluate the ageold decision of using a single, central clock and instead turn to asynchronous or globally asynchronous, locally synchronous (GALS) designs. Communication between synchronous and asynchronous subsystems is difficult to do reliably and efficiently. In this paper, we review the background for the difficulty—metastability—and study new solutions to two different problems: (1) the synchronizer, which synchronizes a signal that can change at an arbitrary time into an asynchronous handshaking domain; and (2) an asynchronous clock-pulse generator. The most difficult aspect of computer design has always been timing. Many early computers (e.g., the ILLIAC and the DEC PDP-6) were asynchronous; these systems’ designers felt that asynchronous machines were modular because timing issues could be localized to small parts of the machines. As late as the 1980s, asynchronous bus protocols were still common (such as DEC’s UNIBUS and the original SCSI protocol, which is still supported by modern SCSI devices). But the difficulties of crossing from one clock domain to another spelled doom for asynchronous protocols, at least in small systems such as PCs, and today the standard approach is to provide the system designer with a hierarchy of clocks, all driven through “gearboxes” by a single central master. (The gearboxes are circuits that generate slave clocks, which are rational multiples of the master clock.) In larger systems, such as local-area networks, this is impossible, and such systems must cope with having several independent clock domains. The trend in VLSI is that the chips get larger, the clocks get faster, and everything gets more complicated. We can expect that tomorrow’s chips will look like today’s local-area networks: the number of clock cycles required to get from one end of the die to the other will increase dramatically. This means that the gearbox approach will become more and more difficult to maintain, because a single wire might span several clock cycles, and the designer will find it difficult to ensure that, for instance, setup and hold times are maintained. A way to deal with the increasing design complexity of VLSI systems is to bring back asynchrony. Several groups have had considerable success with entirely asynchronous systems [19, 4, 20, 5]; others have pursued the globally asynchronous, locally synchronous (GALS) paradigm, first suggested by Chapiro in 1984 [3]. In either case, the issue of interfacing synchronous and asynchronous domains arises. The authors are with the Computer Science Department of the California Institute of Technology, Pasadena, CA 91125, U.S.A. Synchronous and asynchronous design methodologies are based on a simple principle: design composable subsystems in such a way that if the subsystems’ environments satisfy certain assumptions, then the subsystems themselves will present such environments to their neighbors. For synchronous systems, these assumptions take the form of the circuits’ having to maintain legal logic levels within certain setup and hold times. One might think that “asynchronous” circuits naturally make weaker demands on their environments since the clock has been removed. This is not necessarily so. In all asynchronous design methodologies, the synchronous level and timing requirements are replaced by certain handshaking requirements—requirements on the ordering of signal transitions. This means that sampling a signal from a synchronous system within the asynchronous framework is fraught with difficulty, much like the converse operation of sampling an asynchronous signal within the synchronous framework. With care, however, an asynchronous system can sample an unsynchronized signal with zero probability of synchronization failure. We shall review the main source of trouble: metastability; secondly, we shall investigate efficient solutions to a few typical problems: (1) the synchronizer problem, which is concerned with “absorbing” an arbitrarily varying signal into a four-phase signalling scheme; and (2) implementation of an asynchronous timer without introducing metastability.